Recycled Error Bits: Architectural Support for energy-Efficient and Numerically Accurate Software
Computer perform extensive amount of calculations which is carried out by the floating point hardware. The finite precision of floating point hardware provides a potential for small inaccuracies to result in larger, glaring inaccuracies over the course of a long sequence of computations. Many traditional approaches are used to handle this well-know problem. This includes Maximum Hardware Precision, Mixed Hardware Precision, Emulating Greater Precision with Software, etc. All of these traditional techniques have significant energy and performance overheads drawbacks.
This work may have found a solution to this problem. It provides energy-efficient architectural support for floating point accuracy. For each floating point addition performed, that operation’s rounding error is “recycled”. This error is architecturally visible such that it can be used, whenever desired, by software. A compiler pass is designed to allow software to automatically use this feature. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can (a) achieve accuracy comparable to a 64-bit FPU with performance and energy that are comparable to a 32-bit FPU, and (b) achieve accuracy comparable to an all-software scheme for 128-bit accuracy with far better performance and energy usage.
Avaliable for Non-Exclusive License
Duke File (IDF) Number
- Sorin, Daniel
- Nathan, Ralph
- R. Nathan, B. Anthonio, S. L. Lu, H. Naeimi, D. J. Sorin and X. Sun, "Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy," SC14: International Conference for High Performance Computing, Networking, Storage and Analysis, New Orleans, LA, 2014, pp. 117-127. doi: 10.1109/SC.2014.15
- US Patent 9,335,996
For more information please contact
- Koi, Bethany